Design of pulse power supply for EDM based on FPGA

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Design of pulse power supply for EDM based on FPGA


numerical control electric discharge machining (EDM) machine tool is a special machining tool to realize workpiece precision machining. The pulse power circuit of early EDM machine tools was composed of discrete components or realized by single chip microcomputer. The circuit design of discrete components is complex, and the circuit debugging is difficult. The performance of pulse power supply based on single chip microcomputer or 32-bit embedded CPU has been greatly improved, and it also has high intelligence. However, for different processors, its portability is not very good, and once the hardware circuit is completed, it cannot be changed and upgraded. While adopting field programmable gate array FPGA inherits the advantages of power supply designed by MCU or embedded CPU, it also has some new characteristics. The scheme proposed in this paper adopts the cylone II chip of Altera company, configures the Nios II processor provided by Altera on the chip, and adds the user IP module which can generate PWM written by the user in HDL language to Nios II to generate parametric pulse wave, that is, a new intelligent pulse power supply is proposed

1 principle design of pulse power supply

the pulse power supply circuit of CNC machine tool is mainly composed of five parts: pulse generator, isolation amplification circuit, DC power supply circuit, power amplification circuit and switching circuit. The generation process of discharge pulse is as follows. Firstly, the pulse generator generates high-frequency parameterized pulse signal. After the isolation of optocoupler, the power driving circuit amplifies the power, so as to control the on-off of high-frequency switch tube. The other end of the high-frequency switch tube is connected with a DC power supply, which generates a high-frequency discharge machining pulse power supply through the on-off of the switch tube. Its core part is the design of pulse generator

2 design of embedded pulse generator

only by designing a high-frequency and parameterized pulse generator, the precision and parameterization of pulse processing power supply can be realized. The power supply system adopts the FPGA chip ep2c8q208c7 of cycle II sequence of Altera company with good cost performance. Its logic resources are sufficient to realize the functions of the system

2.1 hardware design of embedded system

a soft core Nios II processor is used in the system, and its type is NIOS/F. Nios II processor is Altera's second generation FPGA embedded processor, and its performance exceeds 200dmips. The process of embedded CPU customization is implemented in Quartus II. Quartus II is an integrated FPGA/CPLD development environment provided by Altera. It can complete the design and Simulation of the system. The whole design process is: graphics or HDL compilation, analysis&synthesis, adapter (filter), simulation, programming file assembler, download configuration to FPGA. In addition to Nios II and some commonly used peripheral IP, there is also a user IP in the system. User IP module pulse for generating PWM_ Generator is implemented by writing state machine in VHDL. One module uses state machine to realize three states: idle, pulse width and inter pulse. The conversion between the three states is determined by the clock input, state control signal and counter state. Generally, after the system is started and enters the pulse width state from the idle state, it will switch between the pulse width and pulse to achieve continuous PWM. Pulse_ Another module of generatot is pulse_ Interface between generator and Avalon bus, through which pulse can be read and written_ The status of registers in the generator module controls the PWM pulse width and the size between pulses. After the user module is written in HDL and compiled and synthesized correctly with quartus, the next step of register header file can be carried out_ regs. H and C functions. What is defined in the file is the access method of the user module, which provides the interface between hardware and software. Finally, HDL file, register file and driver are integrated into a complete user IP with Avalon bus interface in SOPC builder. Combining the user IP with Altera IP can generate a hardware pulse generator. Its structure is shown in Figure 1

the composition process is to add Nios II and pulse in SOPC builder_ generator、uart_ JATG and other modules, and then generate the self customized Nios II kernel in sopcbuilder, and generate it in the project file The NiosII kernel, system clock pin, delay reset, PLL and other modules generated previously are added to the BDF file, and the PWM output pin is assigned to the I/O port of FPGA. The hardware system description will be generated after compilation and synthesis PTF file. All the above hardware circuits are implemented in FPGA chip, which is invisible to the user, so its confidentiality is good. What the user can see outside is only the I/O of the circuit. Since the hardware circuit is implemented by HDL, the system can be upgraded

2.2 software programming implementation

software programming adopts the software compilation environment Nios II ide provided by Altera. Based on the open and extensible Eclipse platform, Nios II ide can not only perfectly combine the general user interface with the best development environment in the industry, but also seamlessly integrate with third-party tools. Nios II ide provides a complete C/c++ software development kit, including a debugger, a project manager and a build tool, and a CFI (common flash interface) compatible flash programmer. Altera provides a real-time operating system (RTOS) with Micrium support. The system can be transplanted without any code modification. Make Nios ii3 The parts of the pendulum shall not be disassembled or replaced at will. Developers can easily realize multi task software development in Nios II ide

the software development process is to create a project file in the IDE, and the hardware system specified by the project is generated in quartus PTF file. The new project will include two libraries, one is the user's API library, the other is the system library, which contains various header files and drivers required by users for software programming. In the user library, C/++ or assembly language can be used to write the implementation function of pulse parameters. After writing, the software project can be compiled and debugged, and the project file of the software can be obtained after the desired results are obtained Elf is downloaded to the development device. If you need to adjust the parameters of pulse and pulse to pulse, you can modify the ratio of pulse width to pulse and the cycle length in the NIOS ide. At the same time, the high and low level of I/O port output can control whether each channel of high-power transistor is turned off or not, so as to control the current, which has very high flexibility. In this way, a new pulse sequence suitable for rough, medium and fine machining can be obtained. The codes for pulse control and parameter control in the user program are as follows:

2.3 system simulation

we can use quartus to simulate the functions of the designed system to verify whether the functions meet the requirements. The simulation results of the circuit after the software files are downloaded to the development board are shown in Figure 2. The pulse width can be seen from the figure_ duration_ Time and pulse_ interval_ The proportional parameter of time and the value of the control register. At the same time, you can also see the cycle length of the input clock of the system, the cycle length of the discharge pulse and other information

3 external circuit design

external circuits mainly include DC power supply, isolation and amplification circuit, high-speed switch circuit and protection circuit. The DC power supply circuit is the output of the mains power through the transformer, rectifier bridge circuit and capacitor filter circuit. The output voltage is +80 V and 120 V, which are used for rough machining and finishing machining respectively. The PWM of the pulse generator is used to control the high-frequency switch tube. In order to prevent the pulse generator from burning out, the FPGA development board should be isolated from the switch tube circuit. The frequency of the power supply is very high, and the common optocoupler will produce waveform distortion. Therefore, the 25m high-speed Optocoupler pc412s is used. The switch adopts VMOS. The advantage of using VMOS is that the switching frequency is high and the current and voltage that it can withstand are relatively large. However, VMOS with small input capacitance should be used, otherwise the speed of power off will be affected. The driving circuit of the switch tube is shown in Figure 3

The base of

q1 is the PWM pulse signal output from the FPGA development board through the optocoupler, which drives Q5 through the later drive circuit, so as to realize the positive and negative power supply in the EDM circuit, which can improve the turning off speed of Q5. Q2 is a low-power VMOS tube, Q3 and Q are used to drive a high-power VMOS, so the power should not be too small. R3 and R4 are used to reduce the oscillation of the system waveform, and their resistance should not be too large. The optional value is 100 Ω

4 conclusion

on the basis of the latest research results in the field of EDM mechanism and embedded technology, and in view of the current research status of power supply in micro EDM machining, a new intelligent EDM pulse power supply is proposed. The pulse accuracy of the power supply can reach 0.2 μ s. It can not be achieved by general discrete software and integrated circuits. If the pulse width and inter pulse size can be parameterized, these settings are carried out in the software, and the FPGA design can be updated with good confidentiality. This new type of pulse electric source operates according to the market. Because of its high discharge frequency, the machining accuracy is improved. Because HDL language and FPGA technology are more and more widely used, this intelligent pulse power supply has good universality. (end)


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